1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the formation of silicided polysilicon features in semiconductor devices.
2. Description of the Related Art
As semiconductor device sizes are scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. One response to the higher density requirements is to use T-shaped gate structures having a narrower base area and a wider gate contact area. Examples of such T-shaped gate structures are described in U.S. Pat. Nos. 6,448,163 and 6,417,084. Among other disadvantages, such structures and the processes for making same use materials that provide insufficient conductivity and are not readily integrated with existing technologies without significant development and optimization costs.
Another solution for making smaller devices is to use improved silicide materials (such as cobalt silicide (CoSi2)) in the formation of the polysilicon device features, such as gates and lines. However, such silicide materials exhibit degraded conductivity when the device widths shrink below certain dimensions. For example, CoSi2 exhibits dramatically increased resistance at lateral poly dimensions below 40 nm where agglomeration and voiding occur. Attempts to overcome these performance limitations by using newer silicide materials, such as nickel silicide (NiSi), raise a variety of integration issues associated with such materials, such as NiSi encroachment and spiking.
Accordingly, a need exists for a semiconductor manufacturing process which provides closer packing density with ease of contacting the gate structures. There is also a need for a fabrication process which avoids performance limitations associated with existing silicide materials at smaller device geometries. In addition, there is a need for extending the usefulness of existing silicide materials to smaller device geometries. There is also a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.